The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundancy circuit.
In a recent semiconductor memory device, a redundancy circuit is arranged to compensate a decrease in yield caused by generation of many defects along with an increase in capacity. The redundancy circuit has a spare memory cell array mounted on a chip in advance. When a defect is found in a bit, row, or column in an inspection step upon manufacturing, the defective portion is replaced with a spare cell to enable all bits to operate correctly, and remove the defect. An example of this redundancy circuit is described in S. Konishi et al., "A 64 Kb CMOS SRAMs", IEEE International Solid-State Circuit Conference Digest of Technical Paper, 1982, pp. 258-259.
In a device having the redundancy arrangement, a selection control mechanism of accessing a spare cell instead of a defective cell upon reception of an address signal that selects the defective cell must be realized.
Some of conventional devices have a control mechanism in which fuse elements are formed with a wiring layer or interconnection, and a fuse element corresponding to a defective cell is blown by irradiating a laser beam thereon, thereby accessing a spare cell. For example, to replace one normal row having a defect with one spare row in a memory cell array having 128 normal rows, seven fuses must be respectively arranged for seven address bits (2.sup.7 =128). When the defective normal row is found, of the seven fuses, corresponding ones are blown, and a defect address is written. In activating the device, an externally input address is compared with the defect address written in the fuses. If these addresses coincide with each other, a spare cell is accessed instead of the defective cell.
When a device with the control mechanism using such a fuse has one spare row for 128 normal rows, seven fuse elements, seven pairs of address comparison circuits, and a spare row decoder circuit must be mounted, and a maximum of seven fusing steps must be performed.
As the capacity of the memory cell array increases, the element area for mounting the fuse element, the comparison circuit, and the spare row decoder circuit increases, and the fusing count in the fusing step also increase. A semiconductor memory device with a capacity of 1 Mbits or more has 1,024 normal rows. If one spare row is prepared for every 128 normal rows, this semiconductor memory device requires eight spare rows. To remedy one defective normal row requires 10 (2.sup.10 =1,024) fuse elements, 10 pairs of address comparison circuits, and a spare row address circuit. Accordingly, this semiconductor memory device requires 80 fuse elements, 80 pairs of address comparison circuits, and a spare row decoder circuit as a whole, and the maximum fusing count increases to 80.
In this conventional device, therefore, the element area and the fusing count undesirably increase with capacity of the semiconductor memory device.
Another example of the conventional semiconductor memory devices is disclosed in Japanese Patent Application No. 4-340354 (Japanese Patent Laid-Open No. 6-195996), in which a defective cell can be replaced with a spare cell without recording each address bit of the defective memory cell. In this device, one defective cell portion can be replaced with a spare cell by mounting one fuse and one fusing operation at most. FIG. 11 shows the circuit arrangement.
One spare row selection line (spare word line) SWL is arranged for 128 normal row selection lines (normal word lines) NWL1 to NWL128. Normal row decoder circuits (row main decoders) RMD1 to RMD128 for selecting the normal rows are arranged, and isolation fuses F1 to F128 are series-connected to the output sides of the normal row decoder circuits RMD1 to RMD128. When a defect is found, a fuse F of the defective row is blown to electrically isolate the output of the normal row decoder circuit RMD from the normal row selection line NWL. The gates of p-channel MOS transistors P1 to P128 for monitoring the voltages of the respective normal row selection lines NWL are connected to the input terminals of word line buffers WB1 to WB128 of the respective normal row selection lines NWL.
Normally, one of the normal row decoder circuits RMD is selected to change its output to low level and turn on the p-channel MOS transistors P1 to P128 having gates connected to this row. A node R1 connected to the drain of the p-channel MOS transistor P is charged to high level. By a NOR gate NOR101 and an inverter IN100 receiving this potential, the spare row selection line SWL is changed to high level and set in a non-selected state.
If a defect exists in one of the 128 normal row selection lines NWL, the corresponding fuse F is blown. The input terminals of the word line buffers WB are charged to high level by p-channel MOS transistors P101 to P228 having drains connected to these input terminals. When an address that selects the defective cell is input, the input terminals of all the word line buffers WB1 to WB128 are charged to high level, all the p-channel MOS transistors P1 to P128 are turned off, and the node R1 changes to low level without being charged. The potential of the node R1 is input to the NOR gate NOR101 and the inverter IN100 to change the spare row selection line SWL to low level, thereby setting it in a selected state.
FIG. 12 shows a circuit in which the switching mechanism to a redundancy circuit for rows is also applied to columns. One input/output interface I/O is arranged for every N (N is an integer of 2 or more) columns, eight input/output interfaces I/O form one block, and each block has one spare column (SC) 203. A switching mechanism to the spare column 203 when one defect exists in a normal column is the same as the above-described switching mechanism for rows, and is disclosed in Japanese Patent Application No. 4-340354 (Japanese Patent Laid-Open No. 6-195996).
The conventional device shown in FIG. 11 or 12 has the following problems. Exemplifying the circuit shown in FIG. 11, selection switching between the normal row selection lines NWL1 to NWL128 and the spare row selection line SWL is performed by the p-channel MOS transistors P101 to P228 which charge the input terminals of the word line buffers WB, the p-channel MOS transistors P1 to P128 which detect the potentials of these input terminals, and the NOR gate NOR101 and the inverter IN100 which logically operate the outputs from the p-channel MOS transistors P1 to P128. However, the selection switching mechanism does not synchronize with a clock signal that defines the access cycle of a memory cell, and operates statically. This arrangement is therefore difficult to apply to a semiconductor memory device required to operate at a high speed. More specifically, upon selecting a word line, that particularly requires high speed in the semiconductor memory device, after the logical operations of the normal row decoder circuits RMD1 to RMD128 are established to confirm the potentials of the output terminals, the p-channel MOS transistors P1 to P128 and P101 to P228, the NOR gate NOR101, and the inverter IN100 statically operate to execute selection. That is, the circuit at this portion operates without synchronizing with the clock signal that defines the timing of internal operation. Further, each transistor performs static operation of holding the potential by maintaining an ON or OFF state over the whole period, unlike dynamic operation in which the transistor is kept on for only a predetermined period, and charges the potential in the capacitance to hold the potential for an OFF period.
The time necessary for operating the circuit at this portion greatly influences the whole word line selection operation, causing an operation delay. This occurs not only in word line selection but also in column line selection shown in FIG. 12, generating an operation delay.